The invention relates to an output circuit driven by a switching element such as a power amplifier employing a pulse width modulation technique. More particularly, the invention pertains to such an output circuit in which the power loss which occurs during switching times of the semiconductor devices of which the stage is formed is minimized.
FIG. 1 is a schematic diagram of an output circuit of a conventional power amplifier of the type employing pulse width modulation. In the circuit shown in FIG. 1, complementary MOS FETs Q.sub.1 and Q.sub.2 have signal channels connected in series with one another between positive and negative power source terminals 1 and 2, respectively. Input signals are applied to the gates of the two MOS FETs. In a common application, both gates receive a common input signal. The juncture point of the transistors Q.sub.1 and Q.sub.2 is connected to a low-pass filter 3 composed of an inductor L.sub.1 and a capacitor C.sub.1. The output from the low-pass filter 3 is coupled to a final output terminal 4.
As indicated by dotted lines in FIG. 1, the MOS FETs Q.sub.1 and Q.sub.2 inherently include diodes D.sub.1 and D.sub.2. Referring to FIG. 2, characteristics of a typical N-channel power MOS FET are shown. The drain-source voltage V.sub.DS is plotted on the abscissa and the drain current I.sub.D on the ordinate. The gate-to-source voltage V.sub.GS is employed as a parameter, with each curve shown in FIG. 2 corresponding to a particular indicated value of V.sub.GS. In these characteristic curves, the diode operation is indicated by the negative region of V.sub.DS.
As described with reference to FIG. 1, in a conventional pulse width modulation power amplifier, it has been the practice to employ a low-pass filter composed of an inductor and a capacitor in the output stage of the amplifier to eliminate the carrier frequency. However, the inductor in this filter produces a reverse current which must be suppressed. Diodes D.sub.1 and D.sub.2 which perform this suppressing function are provided by the MOS FETs Q.sub.1 and Q.sub.2. This provides a very simple circuit construction in that it is not necessary to employ separate diodes. However, the diodes D.sub.1 and D.sub.2 inherently included in the structure of the MOS FETs Q.sub.1 and Q.sub.2 have a long reverse recovery time, which is accompanied by certain disadvantages.
More specifically, it is assumed that the voltage at the juncture point of the MOS FETs Q.sub.1 and Q.sub.2 is a voltage V.sub.1 as shown in FIG. 3A. The forward current i.sub.1 to the MOS FET Q.sub.1 is shown in FIG. 3B, and forward current i.sub.2 to the diode Q.sub.2 is shown in FIG. 3C. Ideal waveforms are indicated by solid lines in FIGS. 3B and 3C. However, due to the fact that the diodes D.sub.1 and D.sub.2 have a long reverse recovery time, typically, several hundred nanoseconds, the current i.sub.1 and i.sub.2 actually appear as shown by the dashed lines in FIGS. 3B and 3C. The presence of these spikes in the waveforms of i.sub.1 and i.sub.2 results in a large power loss at the time of switching. Typically, about 60 to 70% of the total power loss in the output stage is a result of such losses. FIG. 4 graphically shows the output power, power loss in the output stage, and the efficiency of the circuit of FIG. 1.
In view of the above, it is a primary object of the present invention to provide a pulse width modulation power amplifier output stage having a significantly improved efficiency.
More specifically, it is an object of the present invention to provide a pulse width modulation power amplifier employing power MOS FETs in which power losses due to switching are greatly reduced.